The present invention relates to a diffusion preventing barrier layer in integrated circuit dielectric structures and its method of manufacture.
Device scaling and integrated circuit IC miniaturization in general has necessitated the use of low dielectric constants (low-k) materials for the various dielectric layers in a multi-layer integrated circuit structure. With feature sizes of approximately 0.25 microns, the intra-layer or line-to-line capacitance can become the dominant component of parasitic capacitance and can adversely impact the performance of the integrated circuit; while the inter-layer (between two layers in a multi-layer structure) is negligible. As can be appreciated, two metal runners in close proximity of one another in an integrated circuit separated by a dielectric material form a natural capacitor structure, and result in a parasitic capacitance in the integrated circuit. Because the metal runners are formed closer and closer together as IC miniaturization mandates, it is necessary to reduce this capacitance level by reducing the dielectric constant of the dielectric material which forms the dielectric layer of the integrated circuit. One such dielectric material is fluorosilicate glass (FSG). In fabricating FSG, a fluorine-based precursor is often used during the chemical vapor deposition (CVD) process in order to reduce the dielectric constant of the oxide (dielectric) being deposited between the metal runners and forming a particular dielectric layer in a multi-level integrated circuit.
While fluorine precursors reduce the dielectric constant of the dielectric material which in turn reduces intra-layer parasitic capacitance, the presence of fluorine in the form of unbonded or loosely-bounded radicals and ions in the dielectric adversely effects reliability and performance. In particular, fluorine can migrate or diffuse in the dielectric material and attack the metal deposited over the surface of the dielectric. Furthermore, as planarization, often by chemical mechanical polishing (CMP), is used in the fabrication of the VLSI and ULSI structures, the fluorine-doped oxide is often exposed to reactive chemical species during the CMP. This fluorine can readily bond with chemical contaminants, for example hydrogen, which may out-gas during subsequent processing at high temperature. This out-gasing may cause further mechanical reliability problems; for example, delamination of metal or reduced adhesion between the metal and dielectric at a particular level of an integrated circuit. Accordingly, because it is desired to use FSG as an interlayer dielectric, it is necessary to passivate unbonded fluorine, hydrogen and other contaminants that can degrade the adhesion of dielectric and metal prior to the deposition of metal over the dielectric.
Certain techniques have been attempted to curb the ill effects of fluorine in the dielectric material. Such techniques included a thermal treatment of the FSG at elevated temperatures for a relatively short period of time, as well as a furnace anneal in a nitrogen ambient and subsequently an exposure to nitrogen plasma for a short period of time. While heating the wafer at higher temperatures may foster the out-gasing of absorbed water and other materials from the films, it does nothing to passivate the unbonded fluorine or other impurities in the film. Furthermore, furnace annealing and plasma exposure of the film may not result in passivation through the entire thickness of the dielectric. Accordingly, underlying untreated FSG in the dielectric may still be exposed during subsequent planarization processing, even though regions close to the top surface of a FSG may have been appropriately passivated. Accordingly, annealing or treating of the surface of the dielectric is not a viable solution because of potential drawbacks in passivation and/or passivation completeness. While high-density plasma chemical vapor deposition (HDP-CVD) has been used in the deposition of fluorine doped silicon dioxide, the resulting surface is very unstable. Fluorine may react on the surface of the wafer, and in particular, issues of the exposure of the surface to moisture and atmosphere, are particularly problematic.
Accordingly, what is needed is a structure for reducing line-to-line capacitance and its method of manufacture that overcomes the above-captioned shortcomings of the prior art.
The present invention relates to a cap or barrier layer that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking metal runners and traces in subsequent levels of a multi-level integrated circuit structure. The invention of the present disclosure is also drawn to a technique for fabricating the integrated circuit by disposing the diffusion-preventing barrier layer between a first dielectric layer and a metal layer at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiOx, where x is preferably less than 2). The impurity containing dielectric material may be fluorosilicate glass (FSG).